Fan out type wafer level package structure and method of the same

ABSTRACT

To pick and place standard dies on a new base for obtaining an appropriate and wider distance between dies than the original distance of dies on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type package. Moreover, the die may be packaged with passive components or other dies with a side by side structure or a stacking structure.

This is a divisional of U.S. patent application Ser. No. 11/169,722,filed Jun. 30, 2005, currently pending, which is a divisional of U.S.patent application Ser. No. 10/725,933, filed Dec. 3, 2003, currentlypending.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a package for semiconductors, and moreparticularly to a fan out type wafer level package.

2. Description of the Prior Art

The semiconductor technologies are developing very fast, and especiallysemiconductor dies have a tendency toward miniaturization. However, therequirements for the functions of the semiconductor dies have anopposite tendency to variety. Namely, the semiconductor dies must havemore I/O pads into a smaller area, so the density of the pins is raisedquickly. It causes the packaging for the semiconductor dies to becomemore difficult and decrease the yield.

The main purpose of the package structure is to protect the dies fromoutside damages. Furthermore, the heat generated by the dies must bediffused efficiently through the package structure to ensure theoperation the dies.

The earlier lead frame package technology is already not suitablethereof is too high. Hence, a new package technology of BGA (Ball GridArray) has been developed to satisfy the packaging requirement for theadvanced semiconductor dies. The BGA package has an advantage of thatthe spherical pins has a shorter pitch than that of the lead framepackage and the pins is hard to damage and deform. In addition, theshorter signal transmitting distance benefits to raise the operatingfrequency to conform to the requirement of faster efficiency. Forexample, the U.S. Pat. No. 5,629,835 discloses a BGA package, byMahulikar et al; the U.S. Pat. No. 5,239,198 discloses another packagethat the FR4 substrates having a pattern of conductive traces thereonare mounted on a PCB; the Taiwan patent No. 177,766 discloses a fan outtype WLP, by the inventor of the present invention.

Most of the package technologies divide dies on a wafer into respectivedies and then to package and test the die respectively. Another packagetechnology, called “Wafer Level Package (WLP)”, can package the dies ona wafer before dividing the dies into respective dies. The WLPtechnology has some advantages, such as a shorter producing cycle time,lower cost, and no need to under-fill or molding. The U.S. Pat. No.5,323,051, “Semiconductor wafer level package”, is disclosed a WLPtechnology by Adams et al. The technology is described as follow. Asshown in FIG. 1, a die 4 is formed on a surface of a semiconductor wafer2, and a cap wafer 6 with a predetermined pattern of frit glass walls 8as a bonding agent is deposited on a surface of the semiconductor wafer2, such that the die 4 is completely surrounded by the frit glass walls8. Then, a surface of the semiconductor wafer 2 without the die 4 ispolished to reduce the height of the semiconductor wafer 2; the processis generally called “Back Grinding”. The die 4 is hermetically sealed ina cavity of predetermined dimensions formed by a combination of thesemiconductor wafer 2, the cap wafer 6, and the frit glass walls 8. Aplurality of metal traces 10 forms a plurality of electrodes onsemiconductor substrate wafer 2 which provide electrical coupling to die4. A plurality of wires 12 is bonded to a plurality of pads formed onexterior portions of metal traces 10, and extends through hole 14 and iscoupled to external electrical dies (not shown).

As aforementioned, the size of the die is very small, and the I/O padsare formed on a surface of a die in the conventional arts. Therefore,number of the pads is limited and a too short pitch among pads resultsin a problem of signal coupling or signal interface. The solder is alsoto form a solder bridge easily due to the too short pitch among pads.Moreover, the size of die gradually become smaller and the packaged ICof the die does not have standard size by some package technologies(such as chip size package), but test equipment, package equipment, etc.for some fixed sizes die or packages can not be kept on using

SUMMARY OF THE INVENTION

Therefore, the present invention has been made in view of the aboveproblems in the prior arts, and it is an objective of the presentinvention to provide a fan out type wafer level package structure and amethod for manufacturing the same.

Another objective of the present invention is to provide a fan out typewafer level package structure to maintain an appropriate pitch betweentwo adjacent pads of the package structure.

Still another objective of the present invention is to avoid problems ofsignal coupling and signal interface.

Another objective of the present invention is to lower the cost of thepackage structure.

Still another objective of the present invention is to raise the yieldof the package structure.

Another objective of the present invention is to provide packagestructure with a adjustable size to keep on using of test equipment,package equipment, etc. having for some fixed sizes die or packages.

As aforementioned, the present invention provides a process of fan outtype wafer level package. First, a plurality of dies is adhered to anisolating base. A first material layer is formed on the isolating base,wherein a space among the plurality of dies on the isolating base isfilled up with the first material layer, and surfaces of the firstmaterial layer and the plurality of dies are at same level. Then, thefirst material layer is cured. A second material layer is formed on thefirst material layer and the plurality of dies. A partial region of thesecond material layer on pads of the plurality of dies is etched to formfirst openings. Next, the second material layer is cured. Contactconductive layer are formed on the first openings to electricallycoupling with the pads, respectively. A photo resist layer is formed onthe second material layer and the contact conductive layer. A partialregion of the photo resist layer is removed to form a fan out patternand expose the contact conductive layer. After that, conductive linesare formed on the fan out pattern and the conductive lines are coupledwith the contact conductive layer, respectively. The remaining photoresist layer is removed. Following that, an isolation layer is formed onthe conductive lines and the second material layer. A partial region ofthe isolation layer on the conductive lines is removed to forming secondopenings. The isolation layer is cured. Finally, solder balls are weldedon the second openings and the base is sawed to isolate the plurality ofdies.

The present invention also provides a fan out type package structure.The package structure comprises an isolating base, a die, a firstdielectric layer, a second dielectric layer, a contact conductive layer,conductive lines, an isolation layer, and solder balls. The die isadhered to the isolating base. The first dielectric layer is formed onthe isolating base and filled in a space except the die on the isolatingbase, wherein surfaces of the first dielectric layer and the die are atsame level. The second dielectric layer is formed on the firstdielectric layer and the die, and the second dielectric layer has firstopenings on pads of the die. The contact conductive layer is formed onthe first openings to electrically coupling with the pads, respectively.The conductive lines are formed on the second dielectric layer andcorresponding the contact conductive layer, and the conductive lines areextended out from corresponding the contact conductive layer tocorresponding end points, wherein the corresponding end points areinside a surface of the second dielectric layer. The isolation layer isformed on the conductive lines and the second dielectric layer, and theisolation layer has second openings on the conductive lines. The solderballs are welded on the second openings and electrical coupling with theconductive lines, respectively.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a semiconductor wafer level package inthe conventional arts;

FIG. 2A to FIG. 2C are schematic diagrams of using pick & place toreplace standard dies onto a new base;

FIG. 3 is a schematic diagram of forming a first material layer on thebase;

FIG. 4 is a schematic diagram of forming a second material layer on thefirst material layer and the die;

FIG. 5 is a schematic diagram of etching a partial region of the secondmaterial layer on pads of the die to form first openings;

FIG. 6 is a schematic diagram of forming contact conductive layer on thefirst openings;

FIG. 7 is a schematic vertical view diagram of forming conductive lineson fan out pattern formed by a photo resist layer;

FIG. 8 is a schematic lateral view diagram of forming conductive lineson fan out pattern formed by a photo resist layer along a-a′ in FIG. 7;

FIG. 9 is a schematic diagram of forming an isolation layer on theconductive lines and the second material layer;

FIG. 10 is a schematic diagram of one packaged structure according tothe present invention;

FIG. 11 is a schematic diagram of one packaged structure having a dieand a passive component according to the present invention;

FIG. 12 is a schematic diagram of one packaged structure having two diesaccording to the present invention; and

DESCRIPTION OF THE PREFERRED EMBODIMENT

Some sample embodiments of the invention will now be described ingreater detail. Nevertheless, it should be recognized that the presentinvention can be practiced in a wide range of other embodiments besidesthose explicitly described, and the scope of the present invention isexpressly not limited expect as specified in the accompanying claims.

Then, the components of the different elements are not shown to scale.Some dimensions of the related components are exaggerated andmeaningless portions are not drawn to provide a more clear descriptionand comprehension of the present invention.

The essence of the present invention is to pick and place standard dieson a new base for obtaining an appropriate and wider distance betweendies than the original distance of dies on a wafer. Therefore, thepackage structure has a larger size of balls array than the size of thedie to avoid the problem of having too close ball pitch. Moreover, thedie may be packaged with passive components (ex. capacitors) or otherdies with a side by side structure or a stacking structure. The detailedprocess of the present invention will be described below.

A processed silicon wafer with dies is put on a tray and then thethickness of the processed silicon wafer is decreased by back lapping toget a thickness range of 50-300 μm . The processed silicon wafer withthe aforementioned thickness is easily sawed to divide the dies on thewafer into respective dies. The back lapping step may be omitted if theprocessed silicon wafer is not hard to saw without back lapping. Adielectric layer (protection layer) is optionally formed on theprocessed silicon wafer before sawing to protect dies form damages.

The divided dies are tested to choose standard good dies 110 there from.The standard good dies 110 are picked and replaced onto a new base 100with a wider distance between two adjacent dies and adhered to the base100 with an UV curing type and/or heat curing type adhesion materialwith good thermal conductivity (not shown), as shown in FIG. 2A. Theadhesion material is coating on the base 100, and the thickness of theadhesion material is preferably 20-60 μm. When the dies 110 are placedon the adhesion material, the adhesion material is cured by UV light orthermal. The distance between two adjacent dies on the base 100 isarranged wider to have enough space for forming fan out ball array inlater steps. Hence, the present invention can maintain an ideal ballpitch for avoiding problems of signal coupling and signal interface andincrease the number of I/O ports (balls), even the size of dies becomessmaller. The dies 110 have I/O pads 116 on the upper surface (as shownin FIG. 4). Passive components 114 or dies 112 are also placed on anadjacent place of the base 100 to obtain a filtering or other functions,as shown in FIG. 2B and FIG. 2C. The material of the base 100 can beglass, silicon, ceramic, crystal materials, etc. and even have a roundor a rectangular shape. In the present invention, the number of dies andpassive components packaged together are not limited. More than threedies and passive components also can be packaged in the same packagestructure by the present invention. The adhesive material of the presentinvention is preferably good thermal conductive material, so theproblems (such as stress) resulted from the temperature differencebetween the dies 110 and the base 100 can be avoided.

The illustration and the corresponding figure below are made throughsingle die to simplify and provide a more clear descriptioncomprehension of the present invention.

First material layer 120 is formed to fill in the space among the die110 and adjacent dies 110, and the surface of the first material layer120 and the surface of the die 110 are at same level. The material ofthe first material layer 120 can be UV curing type or heating curingtype material. Then, the first material layer 120 is cured by UV orthermal. The first material layer 120 may be formed by a screen printingmethod or a photolithography method. The first material layer 120functions as a buffer layer to reduce a stress due to temperature, etc.The first material layer 120 can be a UV and/or heat curing material,such as silicon rubber, epoxy, resin, BCB, and so on. The aforementionedstructure 102, comprising the base 100, the dies 110, and the firstmaterial layer 120, looks same as a wafer with the dies 110 facingabove.

As shown in FIG. 4, a second material layer 122 is coated on thestructure 102. The material of the second material layer 120 can be UVcuring type or heating curing type material, such as BCB, epoxy,SINR3170 (produced by Shin-Etsu Chemical Co.,Ltd.), and so on. Then, thepartial area of the second material layer 122 on the pads 116 of the die110 is removed by using a photo mask to form first openings 124 on thepads 116, and then the second material layer 120 is cured by UV orheating. Next, the plasma etching (RIE) can be used optionally to cleanthe surface of the pads 116 to make sure no residual materials on thepads 116.

The contact conductive layer 126 is formed on the pads 116, as shown inFIG. 6. The preferable material of the contact conductive layer 126 isTi, Cu, or the combination thereof. The contact conductive layer 126 canbe formed by a physical method, a chemical method, or the combinationthereof, for example: CVD, PVD, sputter, and electroplating. A photoresist layer 128 is formed on the second material layer 122 and thecontact conductive layer 126, and then a fan out pattern of the photoresist layer 128 is developed by using a photo mask. The fan out patternhas a plurality of fan out openings starting form the pads 116 to endpoints inside a surface of the second dielectric layer 122,respectively. Namely, the end points of two adjacent fan out openingscan have wider pitches there between than the pitch between two adjacentpads 116. Then, conductive lines 130 by electro plating are formed onthe contact conductive layer 126, as shown in FIG. 7 (vertical view) andFIG. 8 (lateral view, along a-a′ in FIG. 7). The material of theconductive lines 130 are preferably Cu, Ni, Au, or the combinationthereof.

Referring to FIG. 9, the photo resist layer 128 and the contactconductive layer 126 are etched, and then an isolation layer 132 isformed on the conductive lines 130 and the second material layer 122,and the second openings 134 are formed on the conductive lines 130 byusing a photo mask. Next, the first isolation layer 132 is cured. Thefirst isolation layer 132 may be formed by spin coating or screenprinting. The positions of the second openings 134 may be formed abovethe die 110 or the first material layer 120, preferably formed close tothe ending points of the conductive lines 130 respectively, so asuitable distance between two adjacent second openings 134 is to formsolder balls 136 on second openings 134 without the problem of signalcoupling and signal interface.

Referring to FIG. 10, an epoxy layer 140 is formed on the back side ofthe base 100, i.e. on the surface of the base 100 having no die110formed thereon. Then, a top mark is formed on the epoxy layer 140 byusing a photo mask and the epoxy layer 140 is cured. Or using the inkprinting with stencil then heat/UV curing to form a top mark. The topmark is for identified the device name. The step of forming the epoxylayer 140 may be omitted. Next, the solder balls 136 are placed onto thesolder openings 134 and joined the solder balls 136 and the surface ofthe conductive lines 130 with IR re-flow.

Final, the packaged base 100 with the aforementioned structure is sawedalong the sawing line 138 to isolate respective packaged IC. Asaforementioned, the packaged IC may be included passive component 142and the die 110, as shown in FIG. 11. The packaged IC also may be amulti dies with side by side structure, as shown in FIG. 12.

Hence, according to the present invention, the aforementioned packagestructure can maintain an appropriate pitch between two adjacent solderballs of the package structure. Therefore, the present invention canavoid the problems of signal coupling and signal interface. Moreover,the present invention also employs a glass substrate for LCD and thesize of the glass substrate is very larger, so the present invention canlower the cost of the package structure and raise the yield of thepackage structure. Moreover, the package size of the present inventioncan be easily adjusted to test equipment, package equipment, etc.

Although specific embodiments have been illustrated and described, itwill be obvious to those skilled in the art that various modificationsmay be made without departing from what is intended to be limited solelyby the appended claims.

1. A process of fan out type wafer level package, comprising the stepsof: adhering a first plurality of dies to an isolating base; forming afirst material layer on said isolating base to fill in a space amongsaid first plurality of dies on said isolating base; curing said firstmaterial layer; forming a second material layer on said first materiallayer and said first plurality of dies; etching a partial region of saidsecond material layer on first pads of said first plurality of dies toform first openings; curing said second material layer; forming firstcontact conductive layer on said first openings to electrically couplewith said first pads, respectively; forming a first photo resist layeron said second material layer and said first contact conductive layer;removing a partial region of said first photo resist layer to form afirst fan out pattern and expose said first contact conductive layer;forming first conductive lines on said first fan out pattern and saidfirst conductive lines being coupled with said first contact conductivelayer, respectively; removing remaining said first photo resist layer;forming a first isolation layer on said first conductive lines and saidsecond material layer; removing a partial region of said first isolationlayer on said first conductive lines to forming second openings; curingsaid first isolation layer; and welding solder balls on said secondopenings.
 2. The process in claim 1, wherein surfaces of said firstmaterial layer and said first plurality of dies are at same level. 3.The process in claim 1, further comprising a step of sawing said base toisolate said first plurality of dies after the step of said weldingsolder balls.
 4. The process in claim 1, further comprising a step ofadhering a plurality of first passive components to said isolating baseamong said first plurality of dies onto an isolating base before thestep of forming said first material layer.
 5. The process in claim 1,wherein said first plurality of dies comprises at least two types ofdies.
 6. The process in claim 1, wherein said first plurality of dies isformed by sawing a processed silicon wafer.
 7. The process in claim 4,wherein said processed silicon wafer is back lapped to get a thicknessof said processed silicon wafer around 50-300 μm.
 8. The process inclaim 1, wherein materials of said first material layer and said secondmaterial layer comprise UV curing type material, heat curing typematerial, and the combination thereof.
 9. The process in claim 1,further comprising a step of cleaning each surface of said first pads byusing plasma etching after the step of etching a partial region of saidsecond material layer.
 10. The process in claim 1, further comprising astep of forming an epoxy layer on back surface of the base.
 11. Theprocess in claim 1, wherein said first contact conductive layercomprises Ti, Cu, and the combination thereof.
 12. The process in claim1, wherein said first conductive lines comprise Ni, Cu, Au, and thecombination thereof.
 13. The process in claim 1, wherein said isolationlayer comprises epoxy, resin, and the combination thereof.
 14. Theprocess in claim 1, wherein a material of said isolating base is glass,silicon, ceramic, or crystal material.
 15. The process in claim 1,wherein said isolating base is a round type or a rectangular type. 16.The process in claim 1, wherein said first contact conductive layer andsaid first conductive lines are formed by a forming method comprisingphysical method, chemical method, and the combination thereof.
 17. Theprocess in claim 16, wherein said forming method comprising CVD, PVD,sputter, and electroplating.
 18. The process in claim l, wherein thestep of welding said solder balls comprises placing said solder balls onsaid second openings by a screen printing method and joining said solderballs together with surfaces of said first conductive lines by a IRreflow method.
 19. The process in claim 1 further comprising furthersteps before the step of removing a partial region of said firstisolation layer, said further steps being: adhering a second pluralityof dies to said first isolation layer in the vertical direction of saidfirst plurality of dies; forming a third material layer on said firstisolation layer to fill in a space among said second plurality of dieson said first isolation layer; curing said third material layer; forminga fourth material layer on said third material layer and said secondplurality of dies; etching a partial region of said fourth materiallayer on second pads of said second plurality of dies to form thirdopenings; curing said fourth material layer; forming second contactconductive layer on said third openings to electrically coupling withsaid second pads, respectively; removing a partial region of said fourthmaterial layer, said third material layer, and said second materiallayer on said first conductive lines to forming second openings; fillingup said openings with conductive material and surfaces of saidconductive material and said fourth material layer are at same level;forming a second photo resist layer on said fourth material layer, saidconductive material, and said second contact conductive layer; removinga partial region of said second photo resist layer to form a second fanout pattern and expose said second contact conductive layer and saidconductive material; forming second conductive lines on said second fanout pattern and said second conductive lines being coupled withcorresponding said second contact conductive layer and correspondingsaid conductive material; removing remaining said second photo resistlayer; forming a second isolation layer on said second conductive linesand said fourth material layer; removing a partial region of said secondisolation layer on said second conductive lines to forming thirdopenings; curing said second isolation layer; and welding solder ballson said third openings.
 20. The process in claim 19, wherein surfaces ofsaid third material layer and said second plurality of dies are at samelevel
 21. The process in claim 19, further comprising a step of sawingsaid base to isolate packaged dies having one of said first plurality ofdies and one of said second plurality of dies.
 22. The process in claim19, further comprising a step of adhering a second plurality of firstpassive components to said isolating base among said second plurality ofdies onto said first isolation layer before the step of forming saidthird material layer.
 23. The process in claim 19, wherein said secondplurality of dies comprises at least two types of dies.
 24. The processin claim 19, wherein materials of said third material layer and saidfourth material layer comprises UV curing type material, heat curingtype material, and the combination thereof.
 25. The process in claim 19,further comprising a step of cleaning each surface of said second padsby using plasma etching after the step of etching a partial region ofsaid fourth material layer.
 26. The process in claim 19, wherein saidsecond contact conductive layer comprises Ti, Cu, and the combinationthereof.
 27. The process in claim 19, wherein said second conductivelines comprises Ni, Cu, Au, and the combination thereof.
 28. The processin claim 19, wherein said second contact conductive layer and saidsecond conductive lines are formed by a forming method comprisingphysical method, chemical method, and the combination thereof.
 29. Theprocess in claim 19, wherein the step of welding said solder ballscomprises placing said solder balls on said third openings by a screenprinting method and joining said solder balls together with surfaces ofsaid second conductive lines by a IR reflow method.